1. Field of the Invention
The present invention relates to a PLL (Phase-Locked Loop) circuit. More particularly, the present invention relates to the PLL circuit for reducing a phase offset without an increase in an operation voltage.
2. Description of the Related Art
Conventionally, a PLL circuit has been known as one of basic techniques used in various fields, for example, such as information processing, communication and the like. This conventional PLL circuit, whose example is shown in FIG. 1, is provided with a phase frequency comparator 50, a charge pump 51, a loop filter 52, a voltage current converter 53, a current control oscillator 54 and a feedback frequency divider 55.
The phase frequency comparator 50 compares a phase and a frequency of an input signal f.sub.REF with those of a feedback signal f.sub.FB outputted from the feedback frequency divider 55, respectively, to generate one of an increase signal UP and a decrease signal DOWN which indicate errors between both the signals. For example, a clock signal from an oscillator (not shown) is used as the input signal f.sub.REF The increase signal UP generated by the phase frequency comparator 50 has a pulse width corresponding to a phase delay and a frequency drop of the feedback signal f.sub.FB with respect to the input signal f .sub.REF. Also, the decrease signal DOWN has a pulse width corresponding to a phase advance or leading and a frequency rise or increase of the feedback signal f.sub.FB with respect to the input signal f.sub.REF. The increase signal UP and the decrease signal DOWN which are generated by the phase frequency comparator 50 are sent to the charge pump 51.
The charge pump 51 is a charge pump of a single output. The charge pump 51 generates the current pulses corresponding to the respective pulse widths of the increase signal UP and the decrease signal DOWN to send to the loop filter 52. The loop filter 52 has a resistor R.sub.2 and capacitors C.sub.4, C.sub.5. The loop filter 52 accumulates charges in the capacitors C.sub.4, C.sub.5, in response to the current pulses sent by the charge pump 51, and discharges the charges accumulated in the capacitors C.sub.4 ,C.sub.5, and then generates the voltages corresponding to the current pulses. The voltages generated by the loop filter 52 are sent to the voltage current converter 53.
The voltage current converter 53 converts the voltage outputted from the loop filter 52 into a current to send to the current control oscillator 54. The current control oscillator 54 generates a signal oscillating at a frequency corresponding to a value of the current sent by the voltage current converter 53. The current control oscillator 54 oscillates at a frequency equal to N times the frequency of the input signal f.sub.REF at a lock state. The signal generated by the current control oscillator 54 is outputted to external portion as an output signal f.sub.OUT of the PLL circuit, and sent to the feedback frequency divider 55. The feedback frequency divider 55 performs a frequency division into 1/N on the output signal f.sub.OUT to generate the feedback signal f.sub.FB and send the feedback signal f.sub.FB to the phase frequency comparator 50.
The operations of the conventional PLL circuit having the above-mentioned configuration will be described below. Let us suppose that a phase of the feedback signal f.sub.FB fed back to the phase frequency comparator 50 from the feedback frequency divider 55 is more delayed than a phase of the input signal f.sub.REF.
In this case, the phase frequency comparator 50 generates the increase signal UP having the pulse width corresponding to the frequency drop and the phase delay to send to the charge pump 51. The charge pump 51 sends out a current corresponding to the increase signal UP, and charges the capacitors C.sub.4, C.sub.5 of the loop filter 52. Thus, the voltage generated by the loop filter 52 is made higher, which thereby increases the current outputted by the voltage current converter 53. This results in a rise of an oscillation frequency of the output signal f.sub.OUT outputted by the current control oscillator 54. Also, a phase of the output signal f.sub.OUT is advanced to thereby approach a phase of the input signal f.sub.REF .
On the other hand, the case in which the phase of the feedback signal F.sub.FB is more advanced than a phase of the input signal f.sub.REF will be described below.
In this case, the phase frequency comparator 50 generates the decrease signal DOWN having the pulse width corresponding to the frequency rise and the phase advance to send to the charge pump 51. So, the charge pump 51 pulls the current corresponding to the decrease signal DOWN, and discharges the capacitors C.sub.4, C.sub.5 of the loop filter 52. Thus, the voltage outputted by the loop filter 52 is made lower, which thereby decreases the current outputted by the voltage current converter 53. This results in the drop in the oscillation frequency of the output signal f.sub.OUT outputted by the current control oscillator 54. Also, the phase of the output signal f.sub.OUT is delayed to thereby approach the phase of the input signal f.sub.REF .
As mentioned above, the PLL circuit always compares the phase and the frequency of the output signal f.sub.OUT with those of the input signal f.sub.REF , respectively. If there is the phase delay or the phase advance in the output signal f.sub.OUT with respect to the input signal f.sub.REF, the feedback control is carried out so as to correct it. If the phase delay or the phase advance is converged within a predetermined range, the phase frequency comparator 50 generates the increase signal UP and the decrease signal DOWN having the same short pulse width. Thus, the amounts of the charges which are charged and discharged in the capacitors C.sub.4, C.sub.5 of the loop filter 52 are equal to each other and balanced so that the PLL circuit becomes at the lock state.
At this lock state, the phase and the frequency of the output signal f.sub.OUT coincide with those of the input signal f.sub.REF, respectively. By the way, the charge pump 51 typically has a dead band, in which the charges are never charged and discharged unless there is a phase difference greater than a certain value, with regard to the relation between the phase difference, namely, the phase delay or the phase advance and the amount of the charge to be charged or discharged. Thus, it is designed such that the increase signal and the decrease signal having the same pulse width are generated even at the lock state.
The configuration example of another conventional PLL circuit will be described below with reference to FIG. 2.
A charge pump 61 used in this PLL circuit is a differential output pump. That is, the charge pump 61 generates a current pulse OUT1 corresponding to a pulse width of an increase signal UP and a current pulse OUT2 corresponding to a pulse width of a decrease signal DOWN, and sends to a first loop filter 62A and a second loop filter 62B, respectively. The configurations and the operations of the first loop filter 62A and the second loop filter 62B are equal to those of the above-mentioned loop filter 52. Then, a voltage current converter 53 converts a potential difference between a signal outputted from the first loop filter 62A and a signal outputted from the second loop filter 62B into a current signal.
According to this PLL circuit, the noise components of a power supply noise, a coupling noise to circuits except the loop filters and the like included in each of the first loop filter 62A and the second loop filter 62B are equal with each other, and the noise as a whole is cancelled out by the voltage current converter 53. That is, the above-mentioned noise has no influence on the potential difference between the first loop filter 62A and the second loop filter 62B, which leads to the merit of generating the PLL circuit strong in the noise.
By the way, in FIGS. 1 and 2, the capacitors C.sub.5, C.sub.5, are mounted so as to weaken a sharp change in a signal waveform caused by a pulse noise or a jitter. Values of capacitances of the capacitors C.sub.5, C.sub.5, are further smaller than those of the capacitors C.sub.4, C.sub.4, respectively.
The above-mentioned explanations are the examples of the typical PLL circuits. A PLL circuit in which the several defects in those conventional PLL circuits are removed is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 8-84073) as a differential current control oscillator having a variable load. FIG. 3 shows the configuration of the main portion of this PLL circuit.
This PLL circuit receives an input signal f.sub.REF serving as a reference clock and a feedback signal f.sub.FB from a feedback frequency divider 55 to output a pair of an increase signal UP and a decrease signal DOWN. Also, differential output signals OUTI, OUT2 outputted from a first charge pump 71A are sent to capacitors C.sub.A C.sub.B of a loop filter 72, respectively, and sent through a voltage current converter 53 to a current control oscillator 54.
On the other hand, a current outputted by a second charge pump 71B is directly outputted to the current control oscillator 54. An oscillation frequency of the current control oscillator 54 is determined by the current from the voltage current converter 53 and the current from the second charge pump 71B. An output signal of the current control oscillator 54 is outputted to external portion as an output signal f.sub.OUT and also sent through the feedback frequency divider 55 to the phase frequency comparator 50 as a feedback signal f.sub.FB.
This PLL circuit has two charge pumps, differently from the PLL circuits shown in FIGS. 1, 2.
When an output current of the charge pump 51 in FIG. 1 is assumed to be I.sub.P, a signal processing in the loop filter 52 can be represented as [I.sub.p.multidot.(R.sub.2 +1/(s.multidot.C.sub.4))=I.sub.P.multidot.R.sub.2 +I.sub.P /(s.multidot.C.sub.4)] as an equation after a Laplace transform in an alternating current theory. A second term on a right side in this equation is an integration term for changing a frequency, and a first term on the right side is a linear term for instantly changing a phase.
On the contrary, in the PLL circuit of FIG. 3, the first charge pump 71A controls the frequency (integration term), and the second charge pump 71B controls the phase (linear term). By the way, as for the linear term, the second charge pump 71B may be designed such that when a gain of the voltage current converter 53 is assumed to be [g.sub.vi ], a current value of [I.sub.P.multidot.R.sub.2.multidot.g.sub.vi ] is directly inputted to the current control oscillator 54.
As mentioned above, since the charge pump is divided into two sections, the resistor elements R.sub.2, R.sub.2 ' are unnecessary which constitute the loop filter 52, 62A or 62B as shown in FIGS. 1, 2. As a result, since an area of a chip for forming a resistor is not required, this provides a merit of largely contributing to an improvement of an integration degree. Usually, a value of the resistor R.sub.2 is in a range between 100 K.OMEGA. and 10 M.OMEGA.. The resistor occupies a region between 100 .mu.m angle and 1 mm angle in the area of the chip. Thus, the fact that this resistor is not required can largely contribute to the improvement of the integration degree.
By the way, the charge pump 51 of the PLL circuit shown in FIG. 1 is constituted, for example, as shown in FIG. 4. In this charge pump 51, a P-channel MOS transistor Q10 is turned on in response to the increase signal UP. Thus, the charges are charged into the capacitance elements (capacitors C.sub.4, C.sub.5) of the loop filter 52 from a power supply V.sub.DD. Also, an N-channel MOS transistor Q11 is turned on in response to the decrease signal DOWN. Hence, the charges accumulated in the capacitance elements of the loop filter 52 are discharged.
However, this conventional charge pump 51 has the following problem.
At the lock state, the pulse width of the increase signal UP is equal to that of the decrease signal DOWN. Thus, the amount of the charges charged into the capacitance elements of the loop filter 52 should be equal to the amount of the charges discharged from the capacitance elements. However, the problem lies in a fact that the amounts are different from each other because of the following two reasons.
The first reason is as follows.
That is, when the P-channel MOS transistor Q10 acting as a switch is turned on, a voltage applied between a source and a drain of a P-channel MOS transistor Q9 acting as a constant current source is changed depending on the voltage of the loop filter 52. Similarly, when the N-channel MOS transistor Q11 acting as a switch is turned on, a voltage applied between a source and a drain of an N-channel MOS transistor Q12 acting as a constant current source is changed depending on the voltage of the loop filter 52. In any case, the amount of the charges flowing into the loop filter 52 in a unit time, or the amount of the charges flowing out from the loop filter 52 in the unit time is changed depending on the voltage of the loop filter 52. Here, as for the amounts changed depending on the voltage of the loop filter 52 with regard to the amounts of the charges, the changed amount on the side of the P-channel MOS transistor Q9 connected to the power supply V.sub.DD is directionally opposite to the charged amount on the side of the N-channel MOS transistor Q12 connected to a ground. As a result, even if the increase signal UP and the decrease signal DOWN are the pulses having the same length, the amounts of the charges which are charged into and discharged from the capacitance elements of the loop filter 52 are different from each other.
The second reason is as follows.
That is, a factor on a manufacturing process and the like cause respective parasitic capacitances generated in the P-channel MOS transistor and the N-channel MOS transistor to be different from each other. As a result, the amounts of the charges when the charges are charged into or discharged from the parasitic capacitances are changed depending on the output voltage of the loop filter 52, namely, the oscillation frequency. Moreover, they are never cancelled out.
This results in a situation that the capacitance elements of the loop filter 52 is charged, for example, at a substantially excessive state. The occurrence of this situation causes the oscillation frequency to be higher, and also makes the phase of the output signal f.sub.OUT more advanced than that of the input signal f.sub.REF. So, the adjustment is done such that the pulse width of the decrease signal DOWN is made longer, and the amount of the charges discharged from the capacitance elements of the loop filter 52 becomes zero. And, it is balanced at this state. Thus, although the frequency of the input signal f.sub.REF is synchronous with that of the output signal F.sub.OUT, a so-called phase offset is induced in which the phase of the output signal F.sub.OUT is still advanced with respect to that of the input signal f.sub.REF and it becomes at the lock state.
A problem corresponding to the first reason can be solved by using a circuit technique of a cascade connection used in a PLL circuit disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 8-84073). However, the usage of the cascade connection brings about a problem that a high operation voltage must be supplied. So, a PLL circuit is desirable which does not use the cascade connection.
Also, another problem corresponding to the second reason can be solved by configuring a switching circuit with a differential circuit, such as the PLL circuit disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 8-84073). However, the configuration achieves a certain measure of the solution and it is insufficient.
The following technique is disclosed in a paper by Ilya I. Novof, John Austin, Ram Kelkar, Don Strayer, and Steve Wyatt with a title of "Fully Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and .+-. ps Jitter" in the IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, No. 11, NOVEMBER 1995, pp 1259.about.1266. That is to say, a fully integrated phase-locked loop (PLL) in a digital 0.5 .mu.m CMOS technology is described. The PLL has a locking range of 15 to 240 MHz. The static phase error is less than .+-.100 ps with a peak-to-peak jitter of .+-.50 ps at a 100 MHz output frequency. The PLL has a resistorless architecture achieved by the implementation of feedforward current injection into the current controlled oscillator.
The following technique is disclosed in U.S. Pat. No. 5,619,161 (US005619161A) by Novof et al. That is to say, a phase locked loop circuit includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which have no "dead zone". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is provided which reduces jitter in the current controlled oscillator output in the locked phase. Also, a lock indicator is provided which is time independent, and provides a lock indication when the loop enters the locked condition.